The memory field of DRAMs consists of rows, which are also referred to as word lines (WL), and columns, which are also referred to as bit lines (BL). When a memory is accessed, a word line is at first activated. By this, the memory cells arranged in a row are each connected to a bit line in a conducting manner. Thus, the charge of the cell is divided into cell and bit line capacity. Corresponding to the ratio of the two capacities, which is also referred to as transfer ratio, this results in a deflection in the bit line voltage. At the end of the bit line, there is a sense amplifier, which is also referred to as primary sense amplifier (SA), which compares this voltage to the constant voltage on the reference bit line and subsequently amplifies same.
The memory field of DRAMs has redundant elements allowing replacement of defect cells or columns without impeding functionality of the memory chip. If the defect elements exceed the number of redundant elements, the chip will have to be discarded as being “defect.” In order to minimize refusal of memory chips, one tries to sell sub-regions of chips of this kind as smaller size memory chips or lower memory capacity chips. Typically, one tries by using and repairing half the memory region to sell such a “defect” chip as a functional memory chip having half the memory size.
This kind of chip is referred to as “half good” (HG), the process is referred to as HG grading. A full capacity chip is correspondingly referred to as “full good” (FG).
There are two ways of producing HG chips, as is shown in FIG. 5. FIG. 5 shows an exemplary 256-Mbit chip comprising four memory banks bank0-bank3 each comprising a memory capacity of 64 Mbits. If the dark region marked by 1 is repairable, only these regions will be used. Instead of a 256-Mbit chip, the chip will be sold as a 128-Mbit chip. Here, it has the same functionality as a 256-Mbit chip, but a smaller memory capacity of 128 Mbits.
If the light colored region referred to by 0 is still repairable, the 128-Mbit chip will only use the light colored regions.
In order for the 128-Mbit HG chip consisting of a 256-Mbit chip to be compatible with a true 128-Mbit chip, one of the upper row addresses or one of the upper row address bits is not bonded externally, but the chip-internal pad of this row address is clamped to, for example, VCC=1 or VSS=0, depending on the area chosen.
When bit-addressing a 256-Mbit chip, the memory address has an address length of, for example, 28 bits, wherein, for example, the first two bits may be used for addressing the four memory banks and 13 bits (RA1, . . . , RA13) for addressing the individual cells in the memory banks for the row address (RA), and 13 bits (CA1, . . . , CA13) may be available for addressing the columns, referred to as column address (CA).
The more significant the respective address bit clamped to a fixed value, the greater the contiguous memory regions used, referred to as “used HG,” and the contiguous memory regions not used, also referred to as “unused HG.” Since during production, it is typically not only individual memory cells to be defect, but greater areas which are also referred to as error clusters, preferably more significant bits, such as, for example, referring to FIG. 5 the column address or column address bit CA12, are used to select the memory regions used.
More precisely, FIG. 5 thus shows the two ways of a division into used and unused memory regions on the basis of the second most significant column address bit CA12. If CA12 is internally clamped to VCC=1, the dark regions marked by 1 will form the used HG memory region, if CA12 is clamped to VSS=0 or ground (GND), the light regions marked by 0 will form the used memory region.
In order to further increase the HG yield, one may use redundant rows or word lines from the unused regions of an HG chip for repairing defect elements in the used region of the HG chip. This means that, for an HG chip using the dark region marked by 1 in FIG. 5, defect rows can be repaired by redundant rows which are physically in the light unused HG memory region.
The failure probability of semiconductors or semiconductor devices is particularly high in the first weeks after production and at the end of the lifetime, usually after some years. This is expressed by the “bathtub curve” known in semiconductor technology indicating the failure probability of a semiconductor device in dependence on the lifetime or life cycle of the semiconductor device and having a “bathtub shape,” that is it decreases steeply at the beginning, then remains on a low level and increases again steeply at the end of the lifetime. In order to reduce the failure probability of the semiconductor devices in the first weeks, which is also referred to as early failure probability, the semiconductor devices are usually subjected, after production, to a so-called burn in where the devices are subjected to high voltages at high temperatures so as to “age” more quickly. Thus, failing devices may be sorted out before being delivered or used. The remaining elements are of higher reliability.
The redundant rows of unused HG regions are connected to bit lines, which are only stressed to an insufficient degree in stress tests of the 128-Mbit memory in burn in since only addressing the redundant word line causes spreading of this bit line and thus stress for the bit line. All the other word lines along a bit line, which is in the unused HG region, are not used and thus do not generate stress on the bit line.
Thus, the early failure probability discussed above of the bit lines in the unused HG region addressed by the redundant ones increases, since they do not “age” more quickly. This is illustrated in FIG. 6.
FIG. 6 shows the frequency of defects, such as, for example, bit line shorts, also referred to as “BL shorts,” in defects per million (dpm) depending on time.
FIG. 6 shows the early range of the bathtub curve discussed above. The bit lines unstressed or stressed to an insufficient degree during burn in (unstressed BLs) of the unused HG memory region have a considerably higher defect frequency and thus also failure probability than the bit lines stressed during burn in (stressed BLs) of the used HG memory region. The difference is indicated as defect frequency difference (delta dpm).
Additional burn-in time cannot eliminate this problem since the bit lines in the unused HG region are not addressed sufficiently frequently. This is illustrated in FIG. 7.
FIG. 7 shows an exemplary stress ratio between bit lines in the two different memory region types, namely the used memory region (used HG region) and the unused memory region (unused HG region). FIG. 7 shows an example where, out of 1,024 word lines (WL) in the used memory region, four word lines are represented as repaired word lines and are substituted or repaired by means of the inter block repair or inter block redundancy described above by four redundant word lines of the unused memory region. Since burn in is usually performed in rows or words, the result is that the bit lines of the used memory region are stressed 1,024/4=256 times more frequently or longer during burn in than the bit lines in the unused memory region.
The result is a higher early failure rate due to short circuits on used bit lines in unused HG regions.